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Low-Power Variation-Tolerant Design in Nanometer Silicon

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 | #4166011 in Books |  2010-11-24 | Original language:English | PDF # 1 |  9.21 x1.00 x6.14l,1.79 | File type: PDF | 440 pages

||1 of 1 people found the following review helpful.| a very good book on a very relevant topic|By appusom|Being a researcher who has been closely involved in system design with nanoscale silicon, I feel that this book would appeal to students in academia as well as to researchers in the industry. I do not need to emphasize on the importance of the central theme of this book which is simultaneously achieving low-power and robustne|From the Back Cover|Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirement

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspec...

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